TO APPEAR IN : IEEE TRANSACTIONS ON CAD / ICAS 1 On the Generation of Area - Time OptimalTestable

| We present a performance driven generator for integer adders which has the following interesting feature: The generator is parametrized in the operands' bitlength n, the delay of the addition tn and the fault model FM. FM may in particular be chosen as the classical stuck-at fault model, the cellular fault model or the robust path delay fault model. The output of the generator is a performance oriented conditional sum type adder, i.e., an area-minimal n-bit adder of the \conditional sum type" with delay tn (if it exists) together with a small complete test set with respect to the chosen fault model FM. Keywords| Circuit design, design for testability, area-time optimal adders, multidimensional dynamic programming.